The invention relates to a deflection circuit of a cathode ray tube (CRT).
A typical horizontal deflection circuit for a CRT includes a horizontal deflection winding of a deflection yoke coupled in parallel with a retrace capacitance provided by, for example, a retrace capacitor. A horizontal output or switching transistor operating at a horizontal deflection frequency is coupled across the retrace capacitor. A supply voltage is coupled to the switching transistor and to the retrace capacitor via a supply inductance.
For a given deflection winding inductance and a supply voltage magnitude, the effective retrace capacitance required to produce the same deflection current amplitude would have to be smaller when a higher deflection frequency is utilised than when a lower deflection frequency is utilised. Therefore, the flyback pulse voltage developed across a horizontal output transistor would have to be higher at the higher deflection frequency. For a given switching transistor breakdown voltage characteristic, the maximum flyback pulse voltage that is permitted to develop across a horizontal output transistor limits the allowable, maximum horizontal frequency that can be utilised. Therefore, it may be desirable to reduce the effective retrace capacitance without substantially increasing the flyback pulse voltage developed across the horizontal output transistor.
A horizontal deflection circuit, embodying an inventive feature, includes switched, first and second retrace capacitors coupled in series with a deflection winding. First and second switching transistors are coupled across the first and second retrace capacitors, respectively. A supply voltage is coupled via a supply inductance to a junction terminal between the retrace capacitors. The switching transistors are switched off, during retrace, to produce a first retrace pulse voltage across the first retrace capacitance and a second retrace pulse voltage across the second retrace capacitance. The retrace pulse voltage across the deflection winding is equal to the sum of a first retrace pulse voltage and the second retrace pulse voltage and is larger than each. The retrace pulse voltage across the deflection winding is proportional to a ratio of the capacitances of the first and second capacitances. Thereby, capacitive transformation is obtained. Similarly, a voltage across an S-shaping capacitor that is coupled in series with the deflection winding is also proportional to a ratio of the capacitances of the first and second capacitances.
Advantageously, the peak voltage developed across each of the switching transistors is substantially smaller than the sum retrace pulse voltage developed across the deflection winding. The result is that, for a given switching transistor breakdown voltage characteristic, the maximum scan frequency that can be employed is, advantageously, higher than in a deflection circuit in which the entire retrace pulse voltage across the deflection winding is developed across a single switching transistor.
In a video display monitor operating at a frequency selected from a wide range of frequencies, embodying an inventive feature, a feedback control circuit is responsive to a feedback signal that is indicative of the average supply current. A feedback control circuit is used for adjusting the switching timing, during retrace, of one of the switching transistors in a feedback loop relative to that of the other one. The switching timing adjustment is made for obtaining, for example, the same supply current at each of the selected deflection frequencies. Because the average supply current is directly related to the average deflection current, the switching timing adjustment achieves, for example, substantially the same deflection current amplitude using the same supply voltage at each selected deflection frequency. Thereby, gross adjustment of the deflection current is obtained at each selected deflection frequency.
A video display deflection apparatus, embodying an inventive feature, includes a first retrace capacitance and a second retrace capacitance. A deflection winding is coupled to the first and second retrace capacitances to form a resonant circuit, during retrace. A source of a first control signal at a frequency related to a deflection frequency selected from a range of frequencies is provided. A first switching transistor responsive to the first control signal and coupled to said first retrace capacitance is used for generating a first retrace pulse voltage in the first retrace capacitance. A second switching transistor responsive to a second control signal having a variable phase with respect to the first control signal is provided. The second switching transistor is coupled to the second retrace capacitance for generating a second retrace pulse voltage in the second retrace capacitance. The first and the second retrace pulse voltage, are applied to the deflection winding to produce a deflection current in the deflection winding. A controllable phase shifter responsive to a feedback signal, indicative of an amplitude of the deflection current, is provided. The controllable phase shifter is used for varying the phase of the second control signal relative to a phase of the first control signal. A retrace capacitance transformation factor varies in a manner to oppose a tendency of an amplitude of the deflection current to change.